The required capacity of NAND nonvolatile semiconductor memory devices (memories) has been increasing. Efforts have been made to reduce the size of elements in order to increase the capacity of memories. Thus, a sidewall transfer process has frequently been adopted. However, the sidewall transfer process may result in a difference in size between the area between sidewalls between which a core material is sandwiched and the area between sidewalls between which a space is sandwiched. When the area between the sidewalls is processed so as to finally form an active area (AAs) or a control gate electrode (CGs), memory transistors (memory cells) each with a thick AA or CG and a thick charge accumulation layer are formed alternately with memory transistors each with a thin AA or CG and a thin charge accumulation layer. In this case, the impact of inter-cell interference varies among the memory cell transistors. Thus, an increase in variation in threshold during read may result from adoption of a conventional programming scheme such as a lower middle (LM) scheme described in Jpn. Pat. Appln. KOKAI Publication No. 2001-93288. When programming is adapted to suppress a variation in threshold, programming speed cannot disadvantageously be increased.